1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to bipolar transistor structures and methods for their manufacture.
2. Description of the Related Art
FIG. 1 illustrates a conventional single polysilicon bipolar transistor structure 10. Conventional single polysilicon bipolar transistor structure 10 includes a P-type bottom substrate 12, an N-type buried layer 14, and N-type collector region 16, an N-type sink region 18 and a P-type base region 20. The conventional single polysilicon bipolar transistor structure 10 also includes a P-type extrinsic base region 22, and an N-type emitter region 24, both disposed within the P-type base region 20. In addition, the conventional single polysilicon bipolar transistor structure 10 includes shallow trench isolation region 26, field silicon dioxide regions 28, and patterned silicon dioxide (SiO2) layer 30.
In conventional single polysilicon bipolar transistor structure 10, a single N-type patterned polysilicon layer 32 makes contact with the N-type emitter region 24. Furthermnore, base contact 34 is in direct contact with the P-type extrinsic base region 22, emitter contact 36 is in contact with the N-type patterned polysilicon layer 32, and collector contact 38 is in direct contact with the N-type sink region 18. The base contact 34, emitter contact 36 and collector contact 38 each extend through dielectric layer 40.
In order to provide for the base contact 34 to be consistently manufactured in direct contact with the P-type extrinsic base region 22 using standard semiconductor device manufacturing techniques, the P-type extrinsic base region 22 must be relatively large. For example, a base contact with a diameter (i.e., width) of 0.5 microns can require an extrinsic base region that is 1.1 microns wide in order to provide a sufficient alignment tolerance for standard semiconductor device manufacturing techniques.
FIG. 2 illustrates a conventional double polysilicon bipolar transistor structure 50. Conventional double polysilicon bipolar transistor structure 50 includes a P-type bottom substrate 52, an N-type buried layer 54, and N-type collector region 56, an N-type sink region 58 and a P-type base region 60. The conventional double polysilicon bipolar transistor structure 50 also includes a P-type extrinsic base region 62, and an N-type emitter region 64, both disposed within the P-type base region 60. In addition, the conventional double polysilicon bipolar transistor structure 50 includes shallow trench isolation region 65, field silicon dioxide regions 66, and patterned silicon dioxide (SiO2) layer 68.
In conventional double polysilicon bipolar transistor structure 50, a P-type patterned polysilicon layer (a xe2x80x9cpoly 1 layerxe2x80x9d) 70 makes contact with the P-type extrinsic base region 62 and an N-type patterned polysilicon layer (a xe2x80x9cpoly 2 layerxe2x80x9d) 72 makes contact with the N-type emitter region 64. Furthermore, base contact 74 is in contact with the poly 1 layer 70, emitter contact 76 is in contact with the poly 2 layer 72, and collector contact 78 is in direct contact with the N-type sink region 58. The base contact 74, emitter contact 76 and collector contact 78 each extend through dielectric layer 80.
Further descriptions of bipolar transistor structures are available in S. Wolf, Silicon Processing for the VLSI Era, Volume 2-Process Integration, 500-523 (Lattice Press, 1990), which is hereby fully incorporated by reference.
There are drawbacks associated with the aforementioned conventional bipolar transistor structures of FIGS. 1 and 2. First, the relatively large size of the P-type extrinsic base region 22 of conventional single polysilicon bipolar transistor structure 10 necessitates a relatively large base region 20 and, therefore, a relatively large bipolar transistor structure. Second, the relatively large P-type extrinsic base region 22 and P-type base region 20 produce a relatively high extrinsic base region resistance (RB1), a relatively high base region resistance (RB2) and a relatively high collector-base capacitance (CCB). These high resistances and high collector-base capacitance degrade the performance (e.g., speed) of any bipolar transistor devices that include a conventional single polysilicon bipolar transistor structure. The conventional double polysilicon bipolar transistor structure 50, although providing a relatively small P-type extrinsic base region 62, includes two separate patterned polysilicon layers (i.e., the poly 1 layer and the poly 2 layer). The manufacturing of a double polysilicon bipolar transistor structure is, therefore, relatively expensive since it involves the deposition and patterning of two separate polysilicon layers.
Still needed in the field, therefore, is a bipolar transistor structure that is small in size (i.e., compact) and that has a low extrinsic base region resistance, a low base region resistance and a low collector-base capacitance. Also needed is a process for manufacturing such a bipolar transistor structure that is inexpensive and compatible with standard semiconductor device manufacturing techniques.
The present invention provides a bipolar transistor structure that is compact and has a low extrinsic base region resistance, a low base region resistance and a low collector-base capacitance. Bipolar transistor structures according to the present invention include a semiconductor material substrate that has a bottom substrate of a first conductivity type. The semiconductor material substrate also includes a buried layer, a collector region and a sink region, each of a second conductivity type, and a base region of the first conductivity type. The buried layer overlies the bottom substrate, while the collector region overlies the buried layer. The sink region extends from the upper surface of the semiconductor material substrate to the buried layer and is adjacent to the collector region. The base region is disposed overlying the collector region and spaced apart from the sink region.
The semiconductor material substrate also has an extrinsic base region and an emitter region. The extrinsic base region is of the first conductivity type and extends from the upper surface of the semiconductor material substrate into the base region. The emitter region is of the second conductivity type, is spaced apart from the extrinsic base region, and extends from the upper surface of the semiconductor material substrate into the base region. The bipolar transistor structure also includes a single patterned polysilicon layer that at least partially overlies the semiconductor material substrate. The single patterned polysilicon layer includes a first polysilicon portion of the first conductivity type in contact with the extrinsic base region, and a second polysilicon portion of the second conductivity type in contact with the emitter region.
Bipolar transistor structures according to the present invention are compact in size since direct contact to the extrinsic base region is made by the first polysilicon portion, which can be formed to a minimum dimension and self-aligned to the extrinsic base region. Since contact to the extrinsic base region is made by a first polysilicon portion that can be formed to a minimum dimension, the extrinsic base region and base region can also be of a small size, thereby providing a low extrinsic base resistance (RB1), a low base resistance (RB2) and a low collector-base capacitance (CCB).
Also provided is a process for forming a bipolar transistor structure that is inexpensive and compatible with standard semiconductor device manufacturing techniques. The process includes providing a semiconductor material substrate having a bottom substrate and base region of a first conductivity type, as well as a buried layer, collector region and sink region of a second conductivity type. In the semiconductor material substrate, the buried layer overlies the bottom substrate, while the collector region overlies the buried layer. The sink region extends from the upper surface of the semiconductor material substrate to the buried layer and is adjacent to the collector region. In addition, the base region overlies the collector region and is spaced apart from the sink region.
Next, a polysilicon layer is deposited that at least partially overlies the upper surface of the semiconductor material substrate. A first patterned mask layer (e.g., a first patterned photoresist mask) is then formed on the polysilicon layer and dopant ions of the first conductivity type are subsequently implanted into the polysilicon layer using the first patterned mask layer as an implantation mask. The first patterned mask layer is then removed, followed by formation of a second patterned mask layer (e.g., a second patterned photoresist mask) on the polysilicon layer. Dopant ions of the second conductivity type are subsequently implanted into the polysilicon layer using the second patterned mask layer as an implantation mask. The second patterned mask layer is then removed, followed by formation of a third patterned mask layer on the polysilicon layer. Next, the polysilicon layer is etched using the third patterned mask layer as an etch mask to form a patterned polysilicon layer with a first polysilicon portion of the first conductivity type and a second polysilicon portion of the second conductivity type. The semiconductor material substrate and the patterned polysilicon layer are then subjected to a thermal treatment such that dopant ions of the first conductivity type are diffused from the first polysilicon portion into the base region, while dopant ions of the second conductivity type are diffused from the second polysilicon portion into the base region. The dopant ions of the first conductivity type that diffuse into the base region create an extrinsic base region, while the dopant ions of the second conductivity type that diffuse into the collector region create an emitter region that is spaced apart from the extrinsic base region.
Processes according to the present invention are inexpensive since they employ only a single patterned polysilicon layer. In addition, the processes use only standard semiconductor device manufacturing techniques.